What are the disadvantages of an FPGA?

There are many disadvantages to FPGA. A few of them are mentioned below, 

Learning Curve

Novice FPGA developer have to learn new hardware description language (HDL). The most common HDL is VHDL or Verilog. Learning FPGA is becoming easier day by day. There are many blogs, books, and millions of PDF resources are online to get you started.

FPGA Synthesizer Latency

Upon describing the digital logic, the synthesizer takes digital logic and finds the best route to implement in the FPGA. For example, I am using the Nexys 4 DDR board by Xilinx. So I use Vivado 2019.1 IDE. Upon describing the hardware, I click the run synthesis and Vivado IDE takes care of the rest. Figure 1 shows the implementation of the hardware logic. So, each blue square called CLBs. Inside the CLBs are multiplexers, Look Up Table, flip-flip (not the flip-flop you wear).  

Too Fast

Sometimes, being too quick can be a bad thing. If a system needs to run on every second, a timer on seven segment display, the clock needs to be divided to get the desired outcome.

What’s next on the blog?

Sign up to get my blog post regularly. Next, I will give you tips and tricks on how to get started with FPGA. Meanwhile, check out the book “FPGA For Dummies”. Check out this blog for more information on FPGA  “http://fpgafordummy.com/”. 

References

Moore, Andrew. FPGA for Dummies. John Wiley & Sons, Inc, 2017.